As shown in FIG. 1 of Patent Document 1, an N-channel field-effect transistor (MOSFET) disclosed in Patent Document 1 as a semiconductor device includes an N− drain layer 22 on an N+ semiconductor substrate 21, opposing P− field relaxation layers 31 on the N− drain layer 22 that are spaced from one another, a P base region 24 that is on the surface of the field relaxation layer 31 and has a higher concentration than that of the field relaxation layer 31, an N+ source region 26 and a highly-concentrated P+ diffusion layer 25 on the surface of the base region, an N connection region 23a having intermediate concentration between the opposing field relaxation layers 31, and an N− connection region 23b on the surface of the N connection region 23a. 
The semiconductor device disclosed in Patent Document 1 further includes a gate electrode 27 on a part of the source region 26, the base region 24, the field relaxation layer 31, and the N− connection region 23b through a gate oxide film 28a, a source electrode 29 electrically connected to the source region 26, and a drain electrode 30 under an N+ semiconductor substrate 21.
In the semiconductor device having the above structure, when a control voltage is applied to the gate electrode 27 while a voltage is applied between the source electrode 26 and the drain electrode 30, current flows through the channels on the surfaces of the base region 24 and the field relaxation layer 31 below the gate electrode 27.    Patent Document 1: Japanese Patent Publication No. 3484690